Back end of the line (BEOL) and middle of the line (MOL) metallization is becoming more challenging in advanced technology nodes due to the critical dimension (CD) scaling and process capabilities. Also, improved wettability of Copper on Cobalt (Co) and lower resistance of Cobalt over a Ta liner and CuMn alloy seed layer has made Cobalt an excellent liner material for the replacement of Ta liners. For example, Cobalt is becoming a de facto liner and capping layer for BEOL dual damascene copper interconnect metallization processes.
For the MOL plugs (via) and local interconnect metallization, it has been observed that conformal chemical vapor deposition (CVD) tungsten processes provide seams/voids at the center of the features. These seams/voids cause higher contact/interconnect resistance and can become severe due to CD shrinkage in most advanced nodes, e.g., 7 nm technology. In addition, tungsten resistance cannot be reduced with post deposition annealing as it is a refractory metal and does not undergo grain growth or recrystallization at thermal budgets compatible with advanced semiconductor manufacturing. Moreover, the barrier and nucleation layers for tungsten based metallization do not scale to meet the resistance requirements. Therefore, effort has been made to replace the tungsten metallization with Cobalt due to Cobalt's unique void free fill capability which provides a lower resistance over the tungsten metallization.
The introduction of Cobalt for the CMOS local contacts and interconnect and its process integration also has immense challenges at current processing levels, a next level post final RIE wet etch process and/or hard mask removal processes. For example, it has been observed that Cobalt migrates on the surface of dielectric material which is a potential threat for short yield degradation as well as reliability issues (e.g., TDDB). For this reason, it is essential to anchor the Cobalt from migrating to the dielectric surface, which adds additional cost and processing time to the manufacturing process.
Also, in the case of Cobalt being used as a capping layer, it has been observed that Cobalt can easily diffuse to the dielectric capping layers. This diffusion can potentially cause TDDB failures. In the case of Cobalt being used as a liner or a capping layer for dual damascene copper metallization, the post reactive ion etch RIE) clean, e.g., wet cleans, can cause etching of the Cobalt from the liner and the capping layer. Moreover, in the case of complete Cobalt metallization (e.g., TiN/Co fill or TaN/Co fill or TiN or TaN/PVD/CVD Co seed/Co plating), the Cobalt trenches/vias can be etched or corroded during a next level post final RIE wet clean and/or hard mask removal.